US 12,334,771 B2
Circuit failure protection
Amit Vijayvargiya, Karnataka (IN)
Assigned to SANDISK TECHNOLOGIES, INC., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 7, 2023, as Appl. No. 18/349,101.
Claims priority of provisional application 63/385,866, filed on Dec. 2, 2022.
Prior Publication US 2024/0186818 A1, Jun. 6, 2024
Int. Cl. H02J 9/06 (2006.01); G06F 1/26 (2006.01); H02J 7/34 (2006.01)
CPC H02J 9/06 (2013.01) [G06F 1/26 (2013.01); H02J 7/345 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A holdup circuit, comprising:
a boost converter;
a buck converter;
a semiconductor device configured to output a first signal and a second signal;
a first capacitor coupled to the boost converter via a first switch; and
a second capacitor coupled to the boost converter via a second switch, wherein the first switch is controlled by the first signal, wherein the second switch is controlled by the second signal, wherein the first signal is complementary to the second signal, wherein the buck converter is coupled to the first capacitor via a third switch and a first diode, and wherein the buck converter is coupled to the second capacitor via the third switch and a second diode.