US 12,334,721 B2
Overcurrent protection circuit and display device
Ping-lin Liu, Shanghai (CN); and Tong Wu, Shanghai (CN)
Assigned to SEEYA OPTRONICS CO., LTD., Shanghai (CN)
Filed by SEEYA OPTRONICS CO., LTD., Shanghai (CN)
Filed on Jul. 15, 2022, as Appl. No. 17/865,679.
Claims priority of application No. 202111636525.0 (CN), filed on Dec. 29, 2021.
Prior Publication US 2023/0208129 A1, Jun. 29, 2023
Int. Cl. H02H 3/08 (2006.01); H02H 1/00 (2006.01); H02H 3/02 (2006.01); H02H 9/02 (2006.01); H03K 17/082 (2006.01)
CPC H02H 3/08 (2013.01) [H02H 1/0007 (2013.01); H02H 3/02 (2013.01); H03K 17/082 (2013.01)] 19 Claims
OG exemplary drawing
 
1. An overcurrent protection circuit, comprising: a drive transistor, an operational amplifier, a buffer, a peak current detector, and a peak current controller;
wherein
a gate of the drive transistor is electrically connected with a gate control terminal of the buffer, a first electrode of the drive transistor is electrically connected with a first power terminal, and a second electrode of the drive transistor is electrically connected with an output terminal of the overcurrent protection circuit;
an output terminal of the operational amplifier is connected with the buffer, and the operational amplifier controls the drive transistor through the buffer;
an output terminal of the peak current controller is electrically connected with the gate control terminal of the buffer; and
the peak current detector is configured to detect whether an overload current exists at the output terminal of the overcurrent protection circuit; wherein,
in response to the overload current being detected, the overcurrent protection circuit enters a first time period, and the operational amplifier and the peak current controller are configured to jointly control the gate of the drive transistor;
in response to a second time period after the first time period, a main loop controlled by the operational amplifier is disconnected, and the peak current controller is configured to control the gate of the drive transistor;
in response to no overload current being detected, the overcurrent protection circuit enters a third time period, and the operational amplifier and the peak current controller are configured to jointly control the gate of the drive transistor; and
in response to a fourth time period, the operational amplifier is configured to control the gate of the drive transistor.