US 12,334,685 B2
Interconnection system for ground current optimization
Charles Raymond Gingrich, III, Mechanicsburg, PA (US); Scott Eric Walton, Mount Joy, PA (US); and Rutger Wilhelmus Smink, Hamont-Achel (BE)
Assigned to TE Connectivity Solutions GmbH, (CH)
Filed by TE Connectivity Solutions GmbH, Schaffhausen (CH)
Filed on Oct. 28, 2022, as Appl. No. 18/050,569.
Prior Publication US 2024/0145994 A1, May 2, 2024
Int. Cl. H01R 13/6471 (2011.01); H01R 12/72 (2011.01); H01R 13/6587 (2011.01); H01R 13/6588 (2011.01)
CPC H01R 13/6471 (2013.01) [H01R 12/724 (2013.01); H01R 13/6587 (2013.01); H01R 13/6588 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A printed circuit board comprising:
signal contact receiving vias positioned in rows;
ground contact receiving vias positioned in line with the signal contact receiving vias in the rows;
signal integrity vias positioned between the signal contact receiving vias, between the ground contact receiving vias, and between respective signal contact receiving vias and respective ground contact receiving vias;
the signal integrity vias forming a ground fence which reduces cross talk in a foot print of a connector mated with the printed circuit board.