US 12,334,477 B2
Semiconductor packages
Jinnam Kim, Suwon-si (KR); Seokho Kim, Suwon-si (KR); Hoonjoo Na, Suwon-si (KR); and Kwangjin Moon, Suwon-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Dec. 12, 2023, as Appl. No. 18/536,332.
Application 18/536,332 is a continuation of application No. 17/376,784, filed on Jul. 15, 2021, granted, now 11,887,966.
Claims priority of application No. 10-2020-0122861 (KR), filed on Sep. 23, 2020.
Prior Publication US 2024/0136334 A1, Apr. 25, 2024
Prior Publication US 2024/0234377 A9, Jul. 11, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/18 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 25/18 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/48227 (2013.01); H01L 2225/06541 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first structure comprising a first semiconductor chip comprising a first semiconductor integrated circuit; and
a second structure on the first structure,
wherein the second structure comprises a second semiconductor chip comprising a second semiconductor integrated circuit, a semiconductor pattern horizontally spaced apart from the second semiconductor chip and on a side surface of the second semiconductor chip, an insulating pattern between the second semiconductor chip and the semiconductor pattern, and through-electrode structures,
wherein at least one of the through-electrode structures penetrates through at least a portion of the second semiconductor chip or penetrates through the semiconductor pattern, and
wherein the semiconductor pattern has a first side surface facing the side surface of the second semiconductor chip and a second side surface opposing the first side surface, and
wherein the second side surface of the semiconductor pattern is vertically aligned with a side surface of the first semiconductor chip.