US 12,334,476 B2
Semiconductor device with discrete blocks
Ching-Wen Hsiao, Hsinchu (TW); Chen-Shien Chen, Zhubei (TW); Wei Sen Chang, Jinsha Township (TW); and Shou-Cheng Hu, Tai-Chung (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 30, 2023, as Appl. No. 18/525,273.
Application 15/401,851 is a division of application No. 14/886,775, filed on Oct. 19, 2015, granted, now 9,543,278, issued on Jan. 10, 2017.
Application 14/886,775 is a division of application No. 13/608,946, filed on Sep. 10, 2012, granted, now 9,165,887, issued on Oct. 20, 2015.
Application 18/525,273 is a continuation of application No. 17/567,435, filed on Jan. 3, 2022, granted, now 11,855,045.
Application 17/567,435 is a continuation of application No. 16/715,488, filed on Dec. 16, 2019, granted, now 11,217,562, issued on Jan. 4, 2022.
Application 16/715,488 is a continuation of application No. 16/017,060, filed on Jun. 25, 2018, granted, now 10,510,727, issued on Dec. 17, 2019.
Application 16/017,060 is a continuation of application No. 15/401,851, filed on Jan. 9, 2017, granted, now 10,008,479, issued on Jun. 26, 2018.
Prior Publication US 2024/0113080 A1, Apr. 4, 2024
Int. Cl. H01L 29/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/538 (2006.01); H01L 23/64 (2006.01); H01L 25/065 (2023.01); H01L 23/50 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 21/56 (2013.01); H01L 21/6835 (2013.01); H01L 21/6836 (2013.01); H01L 23/3128 (2013.01); H01L 23/3142 (2013.01); H01L 23/481 (2013.01); H01L 23/5222 (2013.01); H01L 23/528 (2013.01); H01L 23/538 (2013.01); H01L 23/5389 (2013.01); H01L 23/64 (2013.01); H01L 24/19 (2013.01); H01L 24/24 (2013.01); H01L 23/50 (2013.01); H01L 2221/68327 (2013.01); H01L 2221/68359 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/02372 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/11002 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/13023 (2013.01); H01L 2224/13024 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/24195 (2013.01); H01L 2224/2518 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06572 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19105 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first planar surface comprising an encapsulant, a first semiconductor device, and a connection block, wherein the first semiconductor device, the encapsulant, and a passive device located within the connection block each have top surfaces which are planar with each other;
a second planar surface comprising the encapsulant, the first semiconductor device and the connection block;
a first redistribution layer located adjacent to the first planar surface; and
a second redistribution layer located adjacent to the second planar surface, wherein the encapsulant, the passive device and the first semiconductor device are each coplanar with each other with respect to respective top and bottom sides as seen in a cross-sectional view.