| CPC H01L 25/0657 (2013.01) [G11C 7/1006 (2013.01); H10B 12/01 (2023.02); G11C 7/1051 (2013.01)] | 11 Claims |
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1. A stacked semiconductor including a stack of a plurality of chips, the stacked semiconductor comprising:
a logic chip; and
a memory unit stacked on the logic chip and including at least one memory chip that is communicable with the logic chip,
wherein the memory chip includes:
at least two memory bodies, each having a memory circuit and provided in parallel in a direction intersecting a stacking direction, and
a connecting portion provided between the memory bodies in a predetermined width and connecting the memory bodies provided in parallel,
wherein the stacked semiconductor further comprises a communication unit provided across the logic chip and the memory chip in the stacking direction,
wherein the memory chip further comprises a plurality of memory chips, and the plurality of memory chips are stacked such that the memory bodies provided in parallel of the memory chip are superimposed on memory bodies of one other memory chip in the stacking direction, and
the communication unit is provided in an aligned manner in the stacking direction in each of the logic chip and the plurality of memory bodies.
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