US 12,334,472 B2
Multiple wafer stack architecture to enable singulation
Omkar Karhade, Chandler, AZ (US); and Sairam Agraharam, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2021, as Appl. No. 17/558,995.
Prior Publication US 2023/0197685 A1, Jun. 22, 2023
Int. Cl. H01L 23/48 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/52 (2006.01); H01L 25/065 (2023.01); H01L 29/40 (2006.01)
CPC H01L 25/0657 (2013.01) [H01L 21/78 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A microelectronic stacked die package structure comprising:
a first die comprising a first conductive layer over a substrate layer;
a second die comprising a first side and a second side, wherein the first side comprises a second conductive layer on the first conductive layer; and
a third die comprising a third conductive layer on the second side of the second die, wherein an edge region of the microelectronic stacked die package structure comprises a first portion over a second portion, the first portion comprising edges of the third die, the second die, and the first conductive layer, and the second portion comprising the substrate layer of the first die, wherein the first portion comprises a curved profile, and the second portion comprises a substantially vertical profile.