US 12,334,471 B2
Semiconductor devices and manufacturing methods of the same
Hyun Mog Park, Seoul (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Oct. 26, 2021, as Appl. No. 17/510,594.
Application 17/510,594 is a continuation of application No. 16/397,556, filed on Apr. 29, 2019, granted, now 11,171,116.
Claims priority of application No. 10-2018-0116804 (KR), filed on Oct. 1, 2018.
Prior Publication US 2022/0045035 A1, Feb. 10, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01); H10B 41/27 (2023.01); H10B 41/30 (2023.01); H10B 41/40 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/40 (2023.01)
CPC H01L 25/0657 (2013.01) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H01L 24/08 (2013.01); H01L 24/89 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H10B 41/27 (2023.02); H10B 41/30 (2023.02); H10B 41/40 (2023.02); H10B 43/27 (2023.02); H10B 43/30 (2023.02); H10B 43/40 (2023.02); H01L 24/05 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80001 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06565 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A method for manufacturing a semiconductor device, comprising:
forming a first substrate structure by forming first gate electrodes stacked and spaced apart from each other in a direction perpendicular to a first surface of a first substrate, first channels extending perpendicular to the first substrate while passing through the first gate electrodes, first bit lines connected to the first channels, and first bonding pads disposed on the first bit lines to be electrically connected to the first bit lines, respectively, on the first substrate;
forming a second substrate structure by forming second gate electrodes stacked and spaced apart from each other in a direction perpendicular to a first surface of a second substrate, second channels extending perpendicular to the second substrate while passing through the second gate electrodes, second bit lines connected to the second channels, and second bonding pads disposed on the second bit lines to be electrically connected to the second bit lines, respectively, on the second substrate;
forming a third substrate structure by forming circuit elements on a third substrate, through contact plugs passing through the third substrate to a predetermined depth, and third bonding pads disposed on the circuit elements, on a first surface of the third substrate;
bonding the third substrate structure to the first substrate structure by bonding the first bonding pads to the third bonding pads;
exposing first ends of the through contact plugs by removing a portion of the third substrate from a second surface of the third substrate, opposite the first surface of the third substrate;
forming fourth bonding pads on the through contact plugs, exposed through the second surface of the third substrate; and
bonding the second substrate structure to the third substrate structure by bonding the second bonding pads to the fourth bonding pads.