US 12,334,462 B2
Semiconductor structure for wafer level bonding and bonded semiconductor structure
Chien-Ming Lai, Tainan (TW)
Assigned to UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed by UNITED MICROELECTRONICS CORP., Hsin-Chu (TW)
Filed on Feb. 1, 2024, as Appl. No. 18/429,477.
Application 18/429,477 is a continuation of application No. 17/382,325, filed on Jul. 21, 2021, granted, now 11,929,335.
Claims priority of application No. 202110652095.5 (CN), filed on Jun. 11, 2021.
Prior Publication US 2024/0178171 A1, May 30, 2024
Int. Cl. H01L 23/00 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 24/05 (2013.01); H01L 24/80 (2013.01); H01L 2224/05016 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/351 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure for wafer level bonding, including:
an interconnecting layer on a substrate;
a bonding dielectric layer on the interconnecting layer; and
a bonding pad in the bonding dielectric layer, comprising:
a top surface exposed from the bonding dielectric layer;
a bottom surface opposite to the top surface and physically contacting a dielectric portion of the interconnecting layer; and
a sidewall between the top surface and the bottom surface, wherein a bottom angle between the sidewall and the bottom surface is smaller than 90 degrees, and the bonding pad is not electrically connected to the interconnecting layer.