US 12,334,459 B2
Integrated circuits
Hsien-Wei Chen, Hsinchu (TW); Ming-Fa Chen, Taichung (TW); Sung-Feng Yeh, Taipei (TW); and Ying-Ju Chen, Yunlin County (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Oct. 20, 2022, as Appl. No. 17/969,694.
Application 17/969,694 is a continuation of application No. 16/859,914, filed on Apr. 27, 2020, granted, now 11,495,559.
Prior Publication US 2023/0040077 A1, Feb. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/40 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/562 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01); H01L 2924/35121 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a conductive pad, comprising at least one dielectric pattern therein, wherein the at least one dielectric pattern penetrates a surface of the conductive pad; and
a through via in a substrate, wherein the conductive pad is electrically connected to the through via through a conductive via between the through via and the conductive pad.