US 12,334,453 B2
Soldered metallic reservoirs for enhanced transient and steady-state thermal performance
Nicholas Neal, Scottsdale, AZ (US); Nicholas S. Haehn, Mesa, AZ (US); Sergio Chan Arguedas, Chandler, AZ (US); Edvin Cetegen, Chandler, AZ (US); Jacob Vehonsky, Gilbert, AZ (US); Steve S. Cho, Chandler, AZ (US); Rahul Jain, Gilbert, AZ (US); Antariksh Rao Pratap Singh, Gilbert, AZ (US); Tarek A. Ibrahim, Mesa, AZ (US); and Thomas Heaton, Mesa, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 29, 2023, as Appl. No. 18/216,005.
Application 18/216,005 is a continuation of application No. 16/526,087, filed on Jul. 30, 2019, abandoned.
Prior Publication US 2023/0343723 A1, Oct. 26, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/00 (2006.01); H01L 23/367 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 23/3675 (2013.01); H01L 23/5381 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a package substrate;
a die over the package substrate, the die having a top side above a bottom side, a first sidewall between the top side and the bottom side, and a second sidewall between the top side and the bottom side, the second sidewall laterally opposite the first sidewall;
a plurality of copper bumps on the bottom side of the die, the plurality of copper bumps vertically between the package substrate and the die;
a first discrete thermal block over the package substrate, the first discrete thermal block laterally spaced apart from the first sidewall of the die;
a second discrete thermal block over the package substrate, the second discrete thermal block laterally spaced apart from the second sidewall of the die;
a heat sink vertically over the first discrete thermal block, vertically over the die, and vertically over the second discrete thermal block, the heat sink extending laterally beyond outermost sidewalls of the first discrete thermal block and the second discrete thermal block; and
an interface material vertically between the heat sink and the first discrete thermal block, vertically between the heat sink and the die, and vertically between the heat sink and the second discrete thermal block.