US 12,334,451 B2
Semiconductor package including package substrate with dummy via and method of forming the same
Chin-Hua Wang, New Taipei (TW); Po-Chen Lai, Hsinchu (TW); Chun-Wei Chen, Taoyuan (TW); and Shin-Puu Jeng, Po-Shan Village (TW)
Assigned to Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company Limited, Hsinchu (TW)
Filed on Jul. 11, 2022, as Appl. No. 17/862,040.
Prior Publication US 2024/0014147 A1, Jan. 11, 2024
Int. Cl. H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/60 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/562 (2013.01) [H01L 21/4853 (2013.01); H01L 21/60 (2021.08); H01L 23/3185 (2013.01); H01L 23/49816 (2013.01); H01L 23/5383 (2013.01); H01L 23/5384 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/2919 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package comprising:
a package substrate comprising a dummy via on a first side of the package substrate;
an interposer module on a second side of the package substrate opposite the first side of the package substrate; and
a stiffener ring on the second side of the package substrate and including an edge that is substantially aligned with the dummy via.