US 12,334,449 B2
Selective use of different advanced interface bus with electronic chips
Dheeraj Subbareddy, Portland, OR (US); Ankireddy Nalamalpu, Portland, OR (US); Lai Guan Tang, Tanjung Bungah (MY); and Mahesh K. Kumashikar, Bangalore (IN)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 25, 2020, as Appl. No. 17/033,655.
Prior Publication US 2022/0102281 A1, Mar. 31, 2022
Int. Cl. H01L 23/538 (2006.01); H01L 23/00 (2006.01); H01L 23/14 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5386 (2013.01) [H01L 23/145 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16225 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first die comprising a first interface coupled to input/output ports of the first die, wherein the first interface comprises:
a physical layer having a footprint compatible with a second interface of a second die having a higher bandwidth and compatible with a third interface of a third die having a lower bandwidth; and
a first set of bumps having a first density less dense than a second density of a second set of bumps of the second interface and corresponding to a third density of a third set of bumps of the third interface;
wherein the first die is configured to directly couple to and communicate with the second die based on coupling the first interface to the second interface, wherein the second set of bumps comprises a number of unused bumps when the first interface is directly coupled to the second interface.