US 12,334,447 B2
Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI)
Kristof Darmawikarta, Chandler, AZ (US); Tarek Ibrahim, Mesa, AZ (US); Siddharth Alur, Chandler, AZ (US); Rahul Jain, Gilbert, AZ (US); and Haobo Chen, Gilbert, AZ (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 27, 2019, as Appl. No. 16/455,688.
Prior Publication US 2020/0411441 A1, Dec. 31, 2020
Int. Cl. H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/538 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/76897 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01); H01L 24/06 (2013.01)] 23 Claims
OG exemplary drawing
 
1. A package substrate, comprising:
a bridge die embedded in the package substrate;
a first contact pad outside a perimeter of the bridge die, the first contact pad having an uppermost surface with a surface finish disposed directly thereon, wherein the uppermost surface of the first contact pad is above a top of the bridge die, the first contact pad in a dielectric layer, the dielectric layer over the bridge die;
a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the first via having substantially vertical sidewalls, and the second contact pad having a protruded interconnect structure positioned thereon, wherein the second contact pad has a bottommost surface above the uppermost surface of the first contact pad, and wherein the first via and the lower contact pad coupled to the second contact pad are in the dielectric layer, and the second contact pad is above the dielectric layer; and
a third contact pad outside the perimeter of the bridge die, the third contact pad laterally between but not vertically overlapping with the first contact pad and the second contact pad, and the third contact pad coupled to a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the first via having substantially vertical sidewalls, and the third contact pad having a protruded interconnect structure positioned thereon, wherein the third contact pad has an uppermost surface at the same level as the uppermost surface of the second contact pad, and wherein the first via and the lower contact pad coupled to the third contact pad are in the dielectric layer, and the third contact pad is above the dielectric layer.
 
8. A semiconductor package, comprising:
a package substrate;
a bridge die embedded in the package substrate;
a first contact pad outside of a perimeter of the bridge die, the first contact pad having an uppermost surface with a surface finish disposed directly thereon, wherein the uppermost surface of the first contact pad is above a top of the bridge die, the first contact pad in a dielectric layer, the dielectric layer over the bridge die;
a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, wherein a first protruded interconnect structure is positioned on the first via, and wherein the second contact pad has a bottommost surface above the uppermost surface of the first contact pad, and wherein the first via and the lower contact pad coupled to the second contact pad are in the dielectric layer, and the second contact pad is above the dielectric layer;
a third contact pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via, wherein a second protruded interconnect structure is positioned on the second via;
a fourth contact pad outside the perimeter of the bridge die, the fourth contact pad laterally between but not vertically overlapping with the first contact pad and the second contact pad, and the fourth contact pad coupled to a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the fourth contact pad having a protruded interconnect structure positioned thereon, wherein the fourth contact pad has an uppermost surface at the same level as the uppermost surface of the second contact pad, and wherein the first via and the lower contact pad coupled to the fourth contact pad are in the dielectric layer, and the fourth contact pad is above the dielectric layer;
a first semiconductor die coupled to the package substrate by the first protruded interconnect structure; and
a second semiconductor die coupled to the package substrate by the second protruded interconnect structure.
 
14. A packaged system, comprising:
a printed circuit board (PCB); and
a semiconductor package coupled to the PCB, the semiconductor package comprising:
a package substrate;
a bridge die embedded in the package substrate;
a first contact pad outside a perimeter of the bridge die, the first contact pad having an uppermost surface with a surface finish disposed directly thereon, wherein the uppermost surface of the first contact pad is above a top of the bridge die, the first contact pad in a dielectric layer, the dielectric layer over the bridge die;
a second contact pad inside the perimeter of the bridge die and coupled to the bridge die by a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, wherein a first protruded interconnect structure is positioned on the first via, and wherein the second contact pad has a bottommost surface above the uppermost surface of the first contact pad, and wherein the first via and the lower contact pad coupled to the second contact pad are in the dielectric layer, and the second contact pad is above the dielectric layer;
a third contact pad inside the perimeter of the bridge die, adjacent to the second contact pad, and coupled to the bridge die by a second via, wherein a second protruded interconnect structure is positioned on the second via;
a fourth contact pad outside the perimeter of the bridge die, the fourth contact pad laterally between but not vertically overlapping with the first contact pad and the second contact pad, and the fourth contact pad coupled to a first via, a lower contact pad and a lower via, the first via on the lower pad, and the lower pad on the lower via, and the fourth contact pad having a protruded interconnect structure positioned thereon, wherein the fourth contact pad has an uppermost surface at the same level as the uppermost surface of the second contact pad, and wherein the first via and the lower contact pad coupled to the fourth contact pad are in the dielectric layer, and the fourth contact pad is above the dielectric layer;
a first semiconductor die coupled to the package substrate by the first protruded interconnect structure; and
a second semiconductor die coupled to the package substrate by the second protruded interconnect structure.