US 12,334,445 B2
Method of fabricating a semiconductor package
Myungsam Kang, Hwaseong-si (KR); Youngchan Ko, Seoul (KR); and Taesung Jeong, Osan-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Sep. 12, 2023, as Appl. No. 18/367,039.
Application 18/367,039 is a continuation of application No. 17/183,562, filed on Feb. 24, 2021, granted, now 11,784,129.
Claims priority of application No. 10-2020-0099253 (KR), filed on Aug. 7, 2020.
Prior Publication US 2024/0006325 A1, Jan. 4, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/5383 (2013.01) [H01L 21/4853 (2013.01); H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/3107 (2013.01); H01L 23/49822 (2013.01); H01L 23/49838 (2013.01); H01L 23/5386 (2013.01); H01L 24/20 (2013.01); H01L 2224/211 (2013.01); H01L 2224/214 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of fabricating a semiconductor package, the method comprising:
forming an interposer chip that includes a base layer, a redistribution layer on a first surface of the base layer, and a via that penetrates the base layer, the via being connected to the redistribution layer and exposed on a second surface of the base layer;
providing the interposer chip into a core portion that includes a conductive element and an upper core pad disposed on and contacting an upper surface of the conductive element;
forming a first buildup portion on a top surface of the core portion and the first surface of the base layer, the first buildup portion being connected to the conductive element and the redistribution layer;
forming a second buildup portion on a bottom surface of the core portion and the second surface of the base layer, the second buildup portion being connected to the conductive element and the via;
mounting a plurality of semiconductor chips on the first buildup portion; and
forming on the first buildup portion a molding layer that covers the plurality of semiconductor chips,
wherein the plurality of semiconductor chips are electrically connected to each other through the first buildup portion and the interposer chip,
wherein the redistribution layer includes a chip conductive patter embedded in a chip dielectric laver,
wherein a top surface of the chip conductive pattern is located at the same level as a level of a top surface of the upper core pad, and
wherein a line pattern of the first buildup portion directly contacts the top surface of the chip conductive pattern.