US 12,334,444 B2
Semiconductor package structure and method for forming the same
Po-Hao Chang, New Taipei (TW); Yi-Jou Lin, Hsinchu (TW); and Hung-Chuan Chen, Hsin-Chu (TW)
Assigned to MEDIATEK INC., Hsinchu (TW)
Filed by MediaTek Inc., Hsin-Chu (TW)
Filed on Apr. 12, 2022, as Appl. No. 17/718,454.
Application 17/718,454 is a continuation of application No. 16/661,219, filed on Oct. 23, 2019, granted, now 11,342,267.
Claims priority of provisional application 62/770,861, filed on Nov. 23, 2018.
Prior Publication US 2022/0238446 A1, Jul. 28, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/5381 (2013.01) [H01L 21/4857 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/5383 (2013.01); H01L 24/16 (2013.01); H01L 25/0655 (2013.01); H01L 25/50 (2013.01); H01L 2224/16227 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor package structure, comprising:
a first semiconductor die, comprising:
a first edge;
a second edge opposite the first edge; and
a first metal layer exposed from the second edge;
a second semiconductor die neighboring the first semiconductor die, comprising:
a third edge neighboring the second edge of the first semiconductor die;
a fourth edge opposite the third edge; and
a second metal layer exposed from the third edge;
a first pad disposed on a front side of the first semiconductor die;
a second pad disposed on a front side of the second semiconductor die; and
an inter-die connector disposed between the first metal layer of the first semiconductor die and the second metal layer of the second semiconductor die to form an electrical connection;
wherein the first metal layer of the first semiconductor die is in the electrical connection with the second metal layer of the second semiconductor die, the first pad and the first metal layer are disposed on opposite sides of the front side of the first semiconductor die, the second pad and the second metal layer are disposed on opposite sides of the front side of the second semiconductor die, the inter-die connector comprises a first surface adjacent to the front side of the first semiconductor die and the front side of the second semiconductor die and a second surface away from the front side of the first semiconductor die and the front side of the second semiconductor die, and the second surface of the inter-die connector is lower than a bottom surface of the first metal layer and a bottom surface of the second metal layer.