US 12,334,443 B2
Lithographic cavity formation to enable EMIB bump pitch scaling
Kristof Darmawikarta, Chandler, AZ (US); Hiroki Tanaka, Chandler, AZ (US); Robert May, Chandler, AZ (US); Sameer Paital, Chandler, AZ (US); Bai Nie, Chandler, AZ (US); Jesse Jones, Chandler, AZ (US); and Chung Kwang Christopher Tan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 6, 2024, as Appl. No. 18/434,347.
Application 18/434,347 is a continuation of application No. 17/712,944, filed on Apr. 4, 2022, granted, now 11,929,330.
Application 17/712,944 is a continuation of application No. 15/934,343, filed on Mar. 23, 2018, granted, now 11,322,444, issued on May 3, 2022.
Prior Publication US 2024/0178145 A1, May 30, 2024
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/538 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5381 (2013.01); H01L 23/5385 (2013.01); H01L 24/82 (2013.01); H01L 2224/12105 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An electronic package, comprising:
a first layer;
a second layer over the first layer;
a cavity through the second layer, the cavity including a first portion and a second portion above the first portion, a width of the first portion greater than a width of the second portion;
a bridge substrate in the cavity, an uppermost surface of the second layer above an uppermost surface of the bridge substrate; and
a conductive pillar in the second layer, the conductive pillar laterally spaced apart from the bridge substrate.