US 12,334,441 B2
Semiconductor device and semiconductor layout structure
Li Tang, Hefei (CN); Cheng Chen, Hefei (CN); Yuxia Wang, Hefei (CN); Wei Jiang, Hefei (CN); and Jing Xu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Mar. 25, 2022, as Appl. No. 17/703,994.
Claims priority of application No. 202111564844.5 (CN), filed on Dec. 20, 2021.
Prior Publication US 2023/0197616 A1, Jun. 22, 2023
Int. Cl. H10D 89/00 (2025.01); H01L 23/528 (2006.01); H10D 62/10 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/5286 (2013.01) [H10D 62/106 (2025.01); H10D 89/10 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate of a first type;
a well of a second type, arranged on the substrate of the first type;
multiple transistors of a first type, arranged along a first direction on the well of the second type;
multiple transistors of a second type, arranged along the first direction on the substrate of the first type;
at least one guard ring of a first type, the at least one guard ring of the first type being arranged on the substrate of the first type and being positioned only on a first side of the multiple transistors of the second type; and
at least one guard ring of a second type, the at least one guard ring of the second type being arranged on the well of the second type and being positioned only on the first side of the multiple transistors of the first type; and
wherein the first side is orthogonal to the first direction.