US 12,334,440 B2
Semiconductor structure and manufacturing method thereof
Yongxiang Li, Hefei (CN); and Min-Hui Chang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Aug. 15, 2022, as Appl. No. 17/887,775.
Application 17/887,775 is a continuation of application No. PCT/CN2022/098145, filed on Jun. 10, 2022.
Claims priority of application No. 202210598976.8 (CN), filed on May 30, 2022.
Prior Publication US 2023/0387008 A1, Nov. 30, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01)
CPC H01L 23/5283 (2013.01) [H01L 21/26506 (2013.01); H01L 21/30604 (2013.01); H01L 21/76816 (2013.01); H10B 12/053 (2023.02); H10B 12/34 (2023.02); H10B 12/488 (2023.02)] 13 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor structure, comprising:
providing a substrate;
forming an ion implantation area in the substrate, an upper surface of the ion implantation area having a distance from an upper surface of the substrate;
forming an initial word line trench in the substrate, the initial word line trench extending from the upper surface of the substrate into the ion implantation area; and
widening the initial word line trench to form a word line trench, a width of a bottom of the word line trench being greater than a minimum width of the word line trench;
wherein a width of an upper part of the initial word line trench is less than ½ of a width of an upper part of the word line trench.