US 12,334,439 B2
Interconnect structure in semiconductor devices
Jhon Jhy Liaw, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 7, 2022, as Appl. No. 17/982,045.
Application 17/982,045 is a continuation of application No. 16/846,861, filed on Apr. 13, 2020, granted, now 11,495,537.
Application 16/846,861 is a continuation of application No. 15/935,871, filed on Mar. 26, 2018, granted, now 10,622,306, issued on Apr. 14, 2020.
Prior Publication US 2023/0063623 A1, Mar. 2, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H10D 62/10 (2025.01); H10D 84/85 (2025.01); H10D 89/10 (2025.01)
CPC H01L 23/528 (2013.01) [H01L 23/535 (2013.01); H10D 62/115 (2025.01); H10D 84/853 (2025.01); H10D 89/10 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a gate stack disposed over a substrate, the gate stack oriented lengthwise along a first direction;
a first layer disposed over the gate stack, the first layer including first conductors disposed in a first dielectric layer, the first conductors having a first thickness and a first width, the first thickness being measured in a second direction that is perpendicular to a top surface of the substrate and the first width being measured in the first direction;
a second layer disposed over the first layer, the second layer including second conductors disposed in a second dielectric layer, the second conductors having a second thickness measured in the second direction, the second conductors having a second width in a third direction that is perpendicular to the first direction, the second width being different than the first width;
a third layer disposed over the second layer, the third layer including third conductors disposed in a third dielectric layer, the third conductors having a third thickness and a third width, the third thickness measured in the second direction and the third width measured in the first direction, wherein the second thickness is smaller than both the first thickness and the third thickness;
a first via feature interfacing with the gate stack and one of the first conductors;
a second via feature interfacing with one of the first conductors and one of the second conductors; and
a third via feature interfacing with one of the second conductors and one of the third conductors.
 
9. A device comprising:
a first plurality of gate stacks disposed over a substrate, the first plurality of gate stacks having a first pitch;
a first metallization layer disposed over and electrically coupled to one of the gate stacks from the first plurality of gate stacks, the first metallization layer including first conductive features disposed in a first dielectric layer, the first conductive features having a first thickness, the first thickness being measured in a first direction perpendicular to a top surface of the substrate;
a second metallization layer disposed over and electrically coupled to the first metallization layer, the second metallization layer including second conductive features disposed in a second dielectric layer, the second conductive features having a second thickness measured in the first direction, the second thickness being at least 10% less than the first thickness, the second conductive features have a second pitch that is different than the first pitch;
a first via feature interfacing with the one of the gate stacks from the first plurality of gate stacks and one of the first conductive features; and
a second via feature interfacing with one of the first conductive features and one of the second conductive features.
 
17. A device comprising:
gate stacks disposed over a substrate;
a first layer for routing powerlines disposed over the gate stacks, the first layer including first conductive features disposed in a first dielectric layer, the first conductive features oriented lengthwise along a first direction and having a first thickness and a first width, the first thickness measured in a second direction that is perpendicular to a top surface of the substrate, the first direction being substantially perpendicular to the second direction, the first width measured in a third direction that is substantially perpendicular to the first and second directions;
a second layer for routing frequency signals disposed on the first layer, the second layer including second conductive features disposed in a second dielectric layer, the second conductive features being oriented lengthwise along the third direction, wherein the second conductive features have a second thickness in the second direction that is less than the first thickness and a second width in the first direction that is less than the first width;
a first via feature interfacing with one of the gate stacks and one of the first conductive features; and
a second via feature interfacing with one of the first conductive features and one of the second conductive features.