US 12,334,435 B2
Middle-of-line interconnect structure and manufacturing method
Cheng-Wei Chang, Taipei (TW); Sung-Li Wang, Zhubei (TW); Yi-Ying Liu, Hsinchu (TW); Chia-Hung Chu, Taipei (TW); and Fang-Wei Lee, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 30, 2024, as Appl. No. 18/650,166.
Application 17/875,533 is a division of application No. 16/844,133, filed on Apr. 9, 2020, granted, now 11,462,471, issued on Oct. 4, 2022.
Application 18/650,166 is a continuation of application No. 17/875,533, filed on Jul. 28, 2022, granted, now 12,009,294.
Claims priority of provisional application 62/908,029, filed on Sep. 30, 2019.
Prior Publication US 2024/0282698 A1, Aug. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/522 (2006.01); H01L 21/285 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/28568 (2013.01); H01L 21/76802 (2013.01); H01L 21/76843 (2013.01); H01L 21/76864 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 23/53266 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit device, comprising:
a lower inter-layer dielectric (ILD) layer disposed over a substrate;
a lower conductive plug disposed in the lower ILD layer;
an upper ILD layer disposed over the lower ILD layer; and
an upper conductive plug disposed in the upper ILD layer and comprising a metal core and an intermixing barrier layer disposed along sidewall surfaces of the metal core;
wherein the intermixing barrier layer comprises a material of the metal core and a material of the upper ILD layer, and wherein a bottommost surface of the metal core extends beneath a bottommost surface of the intermixing barrier layer.