US 12,334,429 B2
Co-integrated vertically structured capacitive element and fabrication process
Abderrezak Marzaki, Aix en Provence (FR); Arnaud Regnier, Les Tallades (FR); and Stephan Niel, Meylan (FR)
Assigned to STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed by STMicroelectronics (Rousset) SAS, Rousset (FR); and STMicroelectronics (Crolles 2) SAS, Crolles (FR)
Filed on Mar. 8, 2023, as Appl. No. 18/118,935.
Application 17/226,324 is a division of application No. 16/546,569, filed on Aug. 21, 2019, granted, now 11,004,785, issued on May 11, 2021.
Application 18/118,935 is a continuation of application No. 17/226,324, filed on Apr. 9, 2021, granted, now 11,626,365.
Prior Publication US 2023/0223332 A1, Jul. 13, 2023
Int. Cl. H01L 23/522 (2006.01); H10B 41/35 (2023.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01)
CPC H01L 23/5223 (2013.01) [H10B 41/35 (2023.02); H10D 1/042 (2025.01); H10D 1/043 (2025.01); H10D 1/716 (2025.01)] 9 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a first well and a second well in a semiconductor substrate;
forming a first trench in the first well, wherein the first trench extends vertically and includes a central conductor insulated from the first well by a first insulating layer;
forming a second insulating layer having a first thickness on a top surface of the semiconductor substrate and covering the central conductor in the first trench;
depositing a first polysilicon layer on the second insulating layer;
lithographically patterning the first polysilicon layer to form:
a first polysilicon portion separated from the first well by the first thickness of the second insulating layer, said first polysilicon portion being electrically connected to the central conductor in the first trench to form a first plate of a capacitor, a second plate of the capacitor formed by the first well; and
a second polysilicon portion separated from the second well by the first thickness of the second insulating layer, said second polysilicon portion forming a gate electrode of a MOS transistor; and
forming source and drain regions for said MOS transistor in the second well.