CPC H01L 23/49838 (2013.01) [H05K 1/189 (2013.01); H01L 23/4985 (2013.01); H05K 2201/10128 (2013.01); H05K 2201/1053 (2013.01)] | 19 Claims |
1. An array substrate, comprising:
a substrate comprising a display area and a non-display area surrounding the display area, wherein the non-display area comprises a chip integration area arranged on one side of the display area along a first direction;
a first pad group arranged in the chip integration area, wherein the first pad group comprises a plurality of first pads arranged along a second direction intersecting with the first direction;
at least one second pad group arranged in the non-display area, wherein the second pad group is arranged on at least one side of the chip integration area along the second direction, and each of the at least one second pad group comprises a plurality of second pads arranged along the second direction; and
a plurality of connecting lines configured to electrically connect the second pads with the first pads, wherein lengths of the connecting lines respectively electrically connected to the plurality of second pads in each of the at least one second pad group arranged along a direction away from the first pad group increase,
wherein the plurality of second pads in each of the at least one second pad group comprise a plurality of alternating current (AC) signal pads and a plurality of direct current (DC) signal pads arranged on one side of all of the AC signal pads away from the first pad group.
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