US 12,334,424 B2
Package structure and manufacturing method thereof
Kai-Ming Chiang, Taichung (TW); Wei-Jhan Tsai, Kaohsiung (TW); Sheng-Feng Weng, Taichung (TW); Ching-Yao Lin, New Taipei (TW); Ming-Yu Yen, MiaoLi County (TW); Kai-Fung Chang, Taipei (TW); Chih-Wei Lin, Hsinchu County (TW); and Ching-Hua Hsieh, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Mar. 31, 2022, as Appl. No. 17/709,470.
Prior Publication US 2023/0317585 A1, Oct. 5, 2023
Int. Cl. H01L 23/02 (2006.01); H01L 21/48 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 25/10 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49822 (2013.01) [H01L 21/4857 (2013.01); H01L 21/486 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 23/5389 (2013.01); H01L 24/24 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 25/105 (2013.01); H01L 24/48 (2013.01); H01L 25/0657 (2013.01); H01L 2224/24226 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32235 (2013.01); H01L 2224/48228 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/73267 (2013.01); H01L 2225/0651 (2013.01); H01L 2225/06524 (2013.01); H01L 2225/06568 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1041 (2013.01); H01L 2225/1058 (2013.01); H01L 2225/1094 (2013.01); H01L 2924/182 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A package structure, comprising:
a first redistribution circuit structure, comprising a first metallization layer, a capping layer disposed over the first metallization layer, a second metallization layer and a dielectric layer disposed over the second metallization layer, wherein a first surface of the capping layer has a surface roughness being less than or substantially equal to 2 μm;
a semiconductor die, disposed on the first surface of the capping layer and electrically coupled to the first redistribution circuit structure, wherein the second metallization layer is accessibly revealed by a surface of the dielectric layer facing away from the semiconductor die;
a connecting film, disposed between the semiconductor die and the capping layer of the first redistribution circuit structure, the semiconductor die being thermally coupled to the first metallization layer through the connecting film; and
a second redistribution circuit structure, disposed on and electrically coupled to the semiconductor die, the second redistribution circuit structure being electrically coupled to the first redistribution circuit structure, and the semiconductor die being disposed between the first redistribution circuit structure and the second redistribution circuit structure.