US 12,334,422 B2
Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substrates
Kyle McElhinny, Tempe, AZ (US); Onur Ozkan, Scottsdale, AZ (US); Ali Lehaf, Chandler, AZ (US); Xiaoying Guo, Chandler, AZ (US); Steve Cho, Chandler, AZ (US); Leonel Arana, Phoenix, AZ (US); Jung Kyu Han, Chandler, AZ (US); Srinivas Pietambaram, Chandler, AZ (US); Sashi Kandanur, Chandler, AZ (US); and Alexander Aguinaga, Tempe, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 24, 2021, as Appl. No. 17/484,486.
Prior Publication US 2023/0097624 A1, Mar. 30, 2023
Int. Cl. H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/50 (2006.01); H01L 23/00 (2006.01); H01L 23/12 (2006.01); H01L 25/065 (2023.01)
CPC H01L 23/49811 (2013.01) [H01L 21/4853 (2013.01); H01L 21/50 (2013.01); H01L 23/12 (2013.01); H01L 24/14 (2013.01); H01L 25/0655 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a substrate;
a semiconductor die mounted to the substrate; and
an array of bumps along a passivation layer at an interface between the substrate and the die, the array of bumps to electrically couple the die to the substrate, respective ones of the bumps having a corresponding base defined by a first portion of metal that protrudes away from the passivation layer, the first portion of the metal being a continuous extension of a second portion of the metal that extends through the passivation layer, the first portions of the metal associated with different ones of the bases having different widths, the second portions of the metal associated with the different ones of the bases having a same width.