US 12,334,421 B2
Thermally enhanced electronic packages for GaN power integrated circuits
Daniel M. Kinzer, El Segundo, CA (US); Jason Zhang, Monterey Park, CA (US); and Thomas Ribarich, Laguna Beach, CA (US)
Assigned to Navitas Semiconductor Limited, Dublin (IE)
Filed by Navitas Semiconductor Limited, Dublin (IE)
Filed on Sep. 21, 2021, as Appl. No. 17/448,324.
Application 17/448,324 is a continuation of application No. 17/169,304, filed on Feb. 5, 2021, granted, now 11,145,579.
Claims priority of provisional application 63/077,526, filed on Sep. 11, 2020.
Prior Publication US 2022/0102251 A1, Mar. 31, 2022
Int. Cl. H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01)
CPC H01L 23/49575 (2013.01) [H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 25/16 (2013.01); H01L 2224/48245 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/1425 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electronic device comprising:
a die-attach pad, at least one drain terminal, at least one source terminal and at least one gate terminal; and
a gallium nitride (GaN) semiconductor substrate including a transistor formed therein, the transistor including a gate, a drain and a source, wherein:
the GaN semiconductor substrate is electrically connected to the die-attach pad;
the gate is directly electrically connected to the at least one gate terminal;
the drain is directly electrically connected to the at least one drain terminal; and
the source is directly electrically connected to the at least one source terminal, wherein the at least one source terminal is directly electrically connected to one or more current sense resistors.