US 12,334,415 B2
Through vias with test structure
Tzung-Han Lee, Hefei (CN); and Chih-Cheng Liu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Feb. 16, 2022, as Appl. No. 17/672,757.
Application 17/672,757 is a continuation of application No. PCT/CN2021/116890, filed on Sep. 7, 2021.
Claims priority of application No. 202110935666.6 (CN), filed on Aug. 16, 2021.
Prior Publication US 2023/0046800 A1, Feb. 16, 2023
Int. Cl. H01L 21/768 (2006.01); H01L 21/66 (2006.01); H01L 23/48 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01)
CPC H01L 23/481 (2013.01) [H01L 21/76877 (2013.01); H01L 21/76898 (2013.01); H01L 22/14 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a semiconductor substrate;
a first metal layer located on a surface of the semiconductor substrate, wherein the first metal layer comprises a plurality of bottom metal wires distributed in parallel along a first direction;
a second metal layer located above a surface of the first metal layer, wherein the second metal layer comprises a plurality of top metal wires distributed in parallel along a second direction, and the second direction is perpendicular to the first direction;
an insulating layer located between the first metal layer and the second metal layer, and configured to isolate the first metal layer from the second metal layer; and
at least four vias located in the insulating layer and filled with a conductive material, wherein the conductive material is connected between the first metal layer and the second metal layer.