US 12,334,406 B2
Package with tilted interface between device die and encapsulating material
Ming-Yen Chiu, Zhubei (TW); Hsin-Chieh Huang, Hsinchu (TW); and Ching Fu Chang, Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Apr. 18, 2022, as Appl. No. 17/659,575.
Application 15/924,916 is a division of application No. 15/254,472, filed on Sep. 1, 2016, granted, now 9,922,895, issued on Mar. 20, 2018.
Application 17/659,575 is a continuation of application No. 16/983,419, filed on Aug. 3, 2020, granted, now 11,322,419.
Application 16/983,419 is a continuation of application No. 16/223,783, filed on Dec. 18, 2018, granted, now 10,734,299, issued on Aug. 4, 2020.
Application 16/223,783 is a continuation of application No. 15/924,916, filed on Mar. 19, 2018, granted, now 10,163,745, issued on Dec. 25, 2018.
Claims priority of provisional application 62/332,252, filed on May 5, 2016.
Prior Publication US 2022/0238404 A1, Jul. 28, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/3105 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 21/78 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/10 (2006.01)
CPC H01L 23/3107 (2013.01) [H01L 21/31053 (2013.01); H01L 21/31058 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 21/76895 (2013.01); H01L 21/78 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/481 (2013.01); H01L 24/05 (2013.01); H01L 24/19 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 2224/04105 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05139 (2013.01); H01L 2224/05144 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/73267 (2013.01); H01L 2224/92125 (2013.01); H01L 2224/94 (2013.01); H01L 2225/1035 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10271 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1032 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1436 (2013.01); H01L 2924/1437 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01); H01L 2924/19043 (2013.01); H01L 2924/19102 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure comprising:
a device die comprising:
a semiconductor substrate comprising:
a first vertical edge;
a second vertical edge over the first vertical edge; and
a top surface connecting the first vertical edge to the second vertical edge;
a plurality of dielectric layers over the semiconductor substrate;
a first polymer layer over the plurality of dielectric layers, wherein the first polymer layer comprises opposing curved edges, and the plurality of dielectric layers laterally extend beyond the opposing curved edges of the first polymer layer, and wherein lower portions of the opposing curved edges of the first polymer layer are more vertical than respective upper portions of the opposing curved edges, and wherein the opposing curved edges are comprised in sidewalls of the device die; and
a metal pillar in the first polymer layer; and
a molding compound in contact with both of the first vertical edge and the top surface, wherein the molding compound forms a horizontal interface with the top surface of the semiconductor substrate.