US 12,334,393 B2
Semiconductor structure and method of making the same
Jian Yang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Appl. No. 17/915,989
Filed by ChangXin Memory Technologies, Inc., Hefei (CN)
PCT Filed Jun. 30, 2022, PCT No. PCT/CN2022/102632
§ 371(c)(1), (2) Date Sep. 29, 2022,
PCT Pub. No. WO2023/245712, PCT Pub. Date Dec. 28, 2023.
Claims priority of application No. 202210726492.7 (CN), filed on Jun. 24, 2022.
Prior Publication US 2024/0234202 A1, Jul. 11, 2024
Int. Cl. H10D 62/10 (2025.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 21/768 (2006.01); H10B 12/00 (2023.01); H10D 64/27 (2025.01)
CPC H01L 21/76831 (2013.01) [H01L 21/0223 (2013.01); H01L 21/76237 (2013.01); H10B 12/01 (2023.02); H10D 62/102 (2025.01); H10D 64/513 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor structure, comprising steps of:
providing a substrate having a first trench;
forming a first initial doped region at a bottom of the first trench;
forming a first oxide layer on sidewalls of the first trench by oxidizing the first trench; and
forming a second oxide layer at the bottom of the first trench, wherein a thickness of the first oxide layer is greater than a thickness of the second oxide layer, and wherein an oxidation rate of the first initial doped region is lower than an oxidation rate of the substrate.