US 12,334,392 B2
Multi-height interconnect trenches for resistance and capacitance optimization
Kevin Lai Lin, Beaverton, OR (US); Mauro Kobrinsky, Portland, OR (US); Mark Anders, Hillsboro, OR (US); Himanshu Kaul, Portland, OR (US); and Ram Krishnamurthy, Portland, OR (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Aug. 7, 2019, as Appl. No. 16/534,063.
Prior Publication US 2021/0043500 A1, Feb. 11, 2021
Int. Cl. H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01)
CPC H01L 21/76816 (2013.01) [H01L 23/5283 (2013.01); H01L 23/5226 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An interconnect layer, comprising:
an interlayer dielectric (ILD);
a first interconnect disposed in the ILD along a first track, wherein the first interconnect has a first height;
a second interconnect disposed in the ILD along a second track, wherein the second interconnect has a second height that is less than the first height;
a third interconnect disposed in the ILD along a third track, wherein the third interconnect has a third height that is between the first height and the second height, wherein the second interconnect is laterally between the third interconnect and the first interconnect;
a fourth interconnect disposed in the ILD along a fourth track, wherein the fourth interconnect has the first height, wherein the fourth interconnect is laterally between the second interconnect and the third interconnect;
a fifth interconnect disposed in the ILD along a fifth track, wherein the fifth track has the second height, wherein the fifth interconnect is adjacent to a side of the third interconnect opposite the fourth interconnect, and wherein each of the first interconnect, the second interconnect, the third interconnect, the fourth interconnect, and the fifth interconnect has a bottommost surface above a bottommost surface of the ILD; and
a via through the ILD, the via laterally between the third interconnect and the fourth interconnect.