| CPC H01L 21/76802 (2013.01) [H01L 21/0274 (2013.01); H10D 64/017 (2025.01)] | 20 Claims |

|
1. A semiconductor device, comprising:
a substrate;
a first gate structure disposed on the substrate, wherein the first gate structure comprises a first capping layer and a first underlying layer below the first capping layer; and
a second gate structure disposed on the substrate, wherein the second gate structure comprises a second capping layer and a second underlying layer below the second capping layer,
wherein the material of the first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the first underlying layer and the second underlying layer, wherein the first capping layer, the second capping layer and the second underlying layer comprise a same metal element.
|
|
9. A semiconductor device, comprising:
a substrate;
a first gate structure disposed on the substrate, wherein the first gate structure comprises a first high-k layer, a first work function layer, and a first capping layer sequentially disposed on the substrate; and
a second gate structure disposed on the substrate, wherein the second gate structure comprises a second high-k layer, a second work function layer, and a second capping layer sequentially disposed on the substrate,
wherein the material of the first capping layer and the second capping layer comprise a material having higher resistant to oxygen or fluorine than materials of the second work function layer.
|
|
15. A semiconductor device, comprising:
a substrate;
a first semiconductor nanosheet disposed over the substrate;
a second semiconductor nanosheet disposed over the semiconductor nanosheet; and
a gate stack wrapping the first semiconductor nanosheet and the second semiconductor nanosheet, wherein the gate stack comprises:
a gate fill material surrounding the first semiconductor nanosheet and the second semiconductor nanosheet;
a first barrier layer between the first semiconductor nanosheet and the gate fill material; and
a second barrier layer surrounding the second semiconductor nanosheet and the gate fill material,
wherein the first barrier layer and the second barrier layer are disposed between the first semiconductor nanosheet and the second semiconductor nanosheet.
|