US 12,334,388 B2
Isolation structure and a self-aligned capping layer formed thereon
I-Wen Wu, Hsinchu (TW); Po-Yu Huang, Hsinchu (TW); Chen-Ming Lee, Taoyuan County (TW); Fu-Kai Yang, Hsinchu (TW); and Mei-Yun Wang, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on May 19, 2022, as Appl. No. 17/748,632.
Prior Publication US 2023/0377943 A1, Nov. 23, 2023
Int. Cl. H01L 21/762 (2006.01); H01L 21/28 (2025.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01); H10D 84/83 (2025.01)
CPC H01L 21/76224 (2013.01) [H10D 30/031 (2025.01); H10D 84/83 (2025.01); H01L 21/28247 (2013.01); H10D 30/6735 (2025.01); H10D 64/017 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
providing a workpiece comprising:
an active region protruding from a substrate,
a first placeholder gate and a second placeholder gate over channel regions of the active region, and
a source/drain feature disposed between the channel regions;
removing a portion of the first placeholder gate and a portion of the substrate thereunder to form an isolation trench;
forming a dielectric feature in the isolation trench, wherein a top surface of the dielectric feature is coplanar with a top surface of the second placeholder gate;
replacing the second placeholder gate with a metal gate stack;
selectively recessing the dielectric feature, thereby forming a recessed dielectric feature;
forming a first capping layer directly over the metal gate stack and a second capping layer over the recessed dielectric feature; and
forming a source/drain contact over and electrically coupled to the source/drain feature.