US 12,334,352 B2
Method and system for etch depth control in III-V semiconductor devices
Wayne Chen, Santa Clara, CA (US); Andrew P. Edwards, Santa Clara, CA (US); Clifford Drowley, Santa Clara, CA (US); and Subhash Srinivas Pidaparthi, Santa Clara, CA (US)
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed by SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, Scottsdale, AZ (US)
Filed on Mar. 28, 2024, as Appl. No. 18/619,304.
Application 18/619,304 is a division of application No. 17/356,042, filed on Jun. 23, 2021, granted, now 11,948,801.
Claims priority of provisional application 63/044,693, filed on Jun. 26, 2020.
Prior Publication US 2024/0242969 A1, Jul. 18, 2024
Int. Cl. H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 21/66 (2006.01); H10D 30/01 (2025.01); H10D 30/63 (2025.01); H10D 62/85 (2025.01)
CPC H01L 21/30612 (2013.01) [H01L 21/308 (2013.01); H01L 22/26 (2013.01); H10D 30/021 (2025.01); H10D 30/025 (2025.01); H10D 30/63 (2025.01); H10D 62/8503 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a field-effect transistor (FET) device, the method comprising:
providing a semiconductor substrate structure comprising:
a first epitaxial semiconductor layer coupled to a semiconductor substrate, wherein the first epitaxial semiconductor layer is characterized by a first conductivity type and a first dopant concentration;
a second epitaxial semiconductor layer coupled to the first epitaxial semiconductor layer, wherein the second epitaxial semiconductor layer is characterized by the first conductivity type;
a marker layer over the second epitaxial semiconductor layer;
a third epitaxial semiconductor layer over the marker layer, wherein the third epitaxial semiconductor layer is characterized by the first conductivity type; and
a fourth epitaxial semiconductor layer over the third epitaxial semiconductor layer, wherein the fourth epitaxial semiconductor layer is characterized by the first conductivity type and a second dopant concentration;
forming a hardmask layer coupled to the fourth epitaxial semiconductor layer, wherein the hardmask layer comprises a set of openings operable to expose an upper surface portion of fourth epitaxial semiconductor layer;
etching a portion of the fourth epitaxial semiconductor layer and the third epitaxial semiconductor layer to form a plurality of fins;
etching at least a portion of the marker layer;
detecting the etching of the at least a portion of the marker layer;
epitaxially growing a semiconductor layer in recess regions disposed between adjacent fins of the plurality of fins;
forming a source metal layer on each of the plurality of fins; and
forming a gate metal layer coupled to the semiconductor layer.