US 12,334,342 B2
Pattern fidelity enhancement
Yu-Tien Shen, Tainan (TW); Ya-Wen Yeh, Taipei (TW); Wei-Liang Lin, Hsin-Chu (TW); Ya Hui Chang, Hsinchu (TW); Yung-Sung Yen, New Taipei (TW); Wei-Hao Wu, Hsinchu (TW); Li-Te Lin, Hsinchu (TW); Ru-Gun Liu, Hsinchu County (TW); and Kuei-Shun Chen, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Jul. 30, 2023, as Appl. No. 18/361,878.
Application 17/114,070 is a division of application No. 15/689,172, filed on Aug. 29, 2017, granted, now 10,861,698, issued on Dec. 8, 2020.
Application 18/361,878 is a continuation of application No. 17/114,070, filed on Dec. 7, 2020, granted, now 11,791,161.
Prior Publication US 2023/0369047 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G03F 7/09 (2006.01); G03F 7/11 (2006.01); H01L 21/027 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); G03F 7/20 (2006.01); H01L 21/306 (2006.01)
CPC H01L 21/0273 (2013.01) [G03F 7/09 (2013.01); H01L 21/0337 (2013.01); H01L 21/311 (2013.01); G03F 7/11 (2013.01); G03F 7/20 (2013.01); H01L 21/0274 (2013.01); H01L 21/306 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a hard mask layer over a substrate, the substrate having one or more regions to receive a treatment process;
forming a resist layer over the hard mask layer;
patterning the resist layer to form a plurality of openings in the resist layer, wherein each of the openings is free of concave corners;
performing an opening expanding process to enlarge at least one of the openings in the resist layer, wherein after the performing of the opening expanding process, at least two of the openings merge;
transferring the openings in the resist layer to the hard mask layer; and
performing the treatment process to the one or more regions in the substrate through the openings in the hard mask layer.