| CPC H01L 21/0234 (2013.01) [H01L 21/02532 (2013.01); H01L 21/31111 (2013.01); H10D 30/031 (2025.01); H10D 86/0212 (2025.01)] | 16 Claims |
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1. A processing method comprising:
forming a dielectric film on a substrate surface through a process cycle, the substrate surface having a plurality of fins including a plurality of gates on a superlattice structure, and at least one feature separating each of the plurality of fins, the at least one feature comprising a bottom surface, a first sidewall, and a second sidewall, the process cycle comprising depositing a first flowable low-k dielectric layer directly on the bottom surface, on the first sidewall and on the second sidewall of the at least one feature, the first flowable low-k dielectric layer having a seam within the at least one feature, depositing a plurality of subsequent flowable low-k dielectric layers to fill the at least one feature and have substantially no seam within the at least one feature adjacent to the superlattice structure, and densifying the plurality of subsequent flowable low-k dielectric layers to form the dielectric film, the dielectric film having a dielectric constant (k) of less than about 3; and
etching the dielectric film from the first sidewall and the second sidewall to leave the dielectric film on the bottom surface.
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