US 12,334,242 B2
Coreless electronic substrates having embedded inductors
Sanka Ganesan, Chandler, AZ (US); Sri Chaitra Jyotsna Chavali, Chandler, AZ (US); Robert L. Sankman, Phoenix, AZ (US); Anne Augustine, Chandler, AZ (US); and Kaladhar Radhakrishnan, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2021, as Appl. No. 17/199,005.
Prior Publication US 2022/0293327 A1, Sep. 15, 2022
Int. Cl. H01F 27/26 (2006.01); H01F 27/40 (2006.01); H01F 41/04 (2006.01)
CPC H01F 27/26 (2013.01) [H01F 27/40 (2013.01); H01F 41/041 (2013.01)] 14 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a first magnetic element on only a first dielectric material layer;
a second dielectric material layer over, and in contact with, the first magnetic element and the first dielectric material layer;
a second magnetic element over the first magnetic element, and in contact with a surface of the second dielectric material layer, the second dielectric material layer having a non-zero thickness between the first magnetic element and the second magnetic element; and
an inductor coil over the first magnetic element, in contact with the surface of the second dielectric material layer, and partially embedded within the second magnetic element, wherein the second dielectric material layer has the non-zero thickness between the first magnetic element and the inductor coil.