US 12,334,186 B2
Memory device, memory system and method for operating memory system including command and address training
Jaehyeok Baek, Suwon-si (KR); Hye-Ran Kim, Suwon-si (KR); Min Ho Maeing, Suwon-si (KR); SungYong Cho, Suwon-si (KR); and MoonChul Choi, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Feb. 9, 2023, as Appl. No. 18/166,737.
Claims priority of application No. 10-2022-0071055 (KR), filed on Jun. 10, 2022; and application No. 10-2022-0085641 (KR), filed on Jul. 12, 2022.
Prior Publication US 2023/0402074 A1, Dec. 14, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01); G11C 29/52 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1093 (2013.01); G11C 29/52 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising
a memory device; and
a memory controller configured to transmit a command and address (CA) signal and a data clock signal to the memory device, transmit a data (DQ) signal to the memory device, or receive the DQ signal from the memory device,
wherein the memory device includes,
a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal,
a CA sampler configured to sample the CA signal based on the first division clock signal, and
a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and
the memory controller includes,
a processing circuitry configured to enter CA training in response to receiving the parity error signal.