US 12,334,185 B2
Memory systems and devices that support methods for calibrating input offsets therein
YongHyun An, Suwon-si (KR); Hae Young Chung, Suwon-si (KR); and Soyeong Shin, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Sep. 12, 2023, as Appl. No. 18/465,416.
Claims priority of application No. 10-2023-0028238 (KR), filed on Mar. 3, 2023.
Prior Publication US 2024/0296876 A1, Sep. 5, 2024
Int. Cl. G11C 7/10 (2006.01); G11C 7/14 (2006.01)
CPC G11C 7/1084 (2013.01) [G11C 7/1012 (2013.01); G11C 7/14 (2013.01); G11C 2207/2254 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device comprising:
a memory cell array;
an input/output circuit configured to generate second data in response to sampling first data by comparing the first data against a reference voltage, and further configured to:
generate an offset calibration code corresponding to a first input offset of the input/output circuit based on the second data, prior to receiving a mode register code;
change a gain of an input buffer corresponding to the mode register code after receiving the mode register code; and
calibrate a second input offset corresponding to the changed gain of the input buffer by adjusting a current amount applied to a current element electrically connected to an input terminal of the input buffer based on the offset calibration code and the mode register code; and
control logic configured to provide the mode register code, which includes gain information associated with the input/output circuit, to the input/output circuit.