US 12,334,184 B2
Bus inversion encoder module and bus inversion system including the same
Jong Sun Park, Seoul (KR); Seong Yoon Kang, Seoul (KR); Jun Il Moon, Icheon-si (KR); Myeong Jae Park, Icheon-si (KR); and Byung Kuk Yoon, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR); and KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Filed by SK hynix Inc., Icheon-si (KR); and KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION, Seoul (KR)
Filed on May 16, 2023, as Appl. No. 18/318,637.
Claims priority of application No. 10-2023-0002995 (KR), filed on Jan. 9, 2023.
Prior Publication US 2024/0233784 A1, Jul. 11, 2024
Int. Cl. G11C 7/10 (2006.01); H03K 19/21 (2006.01)
CPC G11C 7/1048 (2013.01) [G11C 7/1063 (2013.01); H03K 19/21 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A bus inversion encoder module configured to use current data, past data, and future data transmitted through a bus and each current data, past data, and future data including a plurality of bits, to determine whether to invert the current data, and
to generate a current flag, a future flag, and coded current data by using the determination whether to invert the current data, an output flag, and the current data.