US 12,334,183 B2
Memory devices including processing-in-memory architecture configured to provide accumulation dispatching and hybrid partitioning
Kevin Skadron, Charlottesville, VA (US); and Marzieh Lenjani, Champaign, IL (US)
Assigned to UNIVERSITY OF VIRGINIA PATENT FOUNDATION, Charlottesville, VA (US)
Filed by UNIVERSITY OF VIRGINIA PATENT FOUNDATION, Charlottesville, VA (US)
Filed on Apr. 25, 2023, as Appl. No. 18/306,531.
Claims priority of provisional application 63/334,844, filed on Apr. 26, 2022.
Prior Publication US 2023/0343373 A1, Oct. 26, 2023
Int. Cl. G11C 7/10 (2006.01); G06F 17/16 (2006.01)
CPC G11C 7/1039 (2013.01) [G06F 17/16 (2013.01); G11C 7/1057 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An integrated circuit memory device comprising:
a plurality of banks of memory, each of the banks of memory including:
a first pair of sub-arrays comprising first and second sub-arrays, the first pair of sub-arrays configured to store data in memory cells of the first pair of sub-arrays;
a first row buffer memory circuit located in the integrated circuit memory device adjacent to the first pair of sub-arrays and configured to store first row data received from the first pair of sub-arrays and configured to transfer the first row data into and/or out of the first row buffer memory circuit; and
a first sub-array level processor circuit in the integrated circuit memory device adjacent to the first pair of sub-arrays and operatively coupled to the first row data, wherein the first sub-array level processor circuit is configured to perform column oriented processing a sparse matrix kernel stored, at least in-part, in the first pair of sub-arrays, with input vector values stored, at least in part, in the first pair of sub-arrays to provide output vector values representing products of values stored in columns of the sparse matrix kernel with the input vector values.