US 12,334,182 B2
Page buffer, memory device, and method for programming thereof
Zhichao Du, Wuhan (CN); Yan Wang, Wuhan (CN); Daesik Song, Wuhan (CN); and Yu Wang, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Jan. 12, 2023, as Appl. No. 18/096,346.
Application 18/096,346 is a continuation of application No. PCT/CN2022/140559, filed on Dec. 21, 2022.
Claims priority of application No. 202210248481.2 (CN), filed on Mar. 14, 2022.
Prior Publication US 2023/0290388 A1, Sep. 14, 2023
Int. Cl. G11C 7/00 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01)
CPC G11C 7/1039 (2013.01) [G11C 7/1063 (2013.01); G11C 7/12 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A page buffer, comprising:
a first charge/discharge circuit coupled to a bit line and configured to
store first bit line forcing information, and
apply a first bit line forcing voltage to the bit line based on the first bit line forcing information; and
a second charge/discharge circuit coupled to the bit line and configured to
store a second bit line forcing information, and
apply a second bit line forcing voltage, different from the first bit line forcing voltage, to the bit line based on the second bit line forcing information;
wherein the first bit line forcing voltage and the second bit line forcing voltage are both higher than a programming bit line voltage and lower than a programming-inhabit bit line voltage.