| CPC G11C 5/063 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 10/125 (2023.02); G11C 11/419 (2013.01)] | 20 Claims |
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1. A memory cell, comprising:
a first transistor of a first type, and being configured as a first pass-gate transistor;
a second transistor of a second type different from the first type, and the second transistor being positioned below the first transistor;
a third transistor of the first type, and being configured as a second pass-gate transistor;
a fourth transistor of the second type, and being positioned below the third transistor;
a first inverter coupled to the first transistor and the third transistor;
a second inverter coupled to the first transistor, the third transistor and the first inverter;
a first word line extending in a first direction, being configured to supply a first word line signal, being on a first metal layer above a front-side of a substrate, and being coupled to the first transistor and the third transistor; and
a second word line extending in the first direction, being configured to supply a second word line signal, being on a second metal layer different from the first metal layer, the second metal layer being below a back-side of the substrate opposite from the front-side of the substrate, and the second word line being coupled to the second transistor and the fourth transistor,
wherein at least the first transistor, the second transistor, the third transistor or the fourth transistor are on the front-side of the substrate.
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