| CPC G11C 5/063 (2013.01) [H01L 25/0657 (2013.01); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 80/00 (2023.02); H01L 2225/06506 (2013.01)] | 16 Claims |

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1. A semiconductor memory device comprising:
a first chip and a second chip bonded via a plurality of bonding electrodes, wherein
the first chip includes a first region and a second region,
the first region includes:
a plurality of memory cells;
a plurality of bit lines connected to the plurality of memory cells;
a plurality of word lines connected to the plurality of memory cells; and
a plurality of first bonding electrodes that are a part of the plurality of bonding electrodes and electrically connected to the plurality of bit lines,
the second region includes:
a plurality of contacts electrically connected to the plurality of word lines; and
a plurality of second bonding electrodes that are a part of the plurality of bonding electrodes and electrically connected to the plurality of contacts,
the plurality of first bonding electrodes include a third bonding electrode and a fourth bonding electrode adjacent in a first direction,
the plurality of second bonding electrodes include a fifth bonding electrode and a sixth bonding electrode adjacent in the first direction, and
a distance from a center position in the first direction of the third bonding electrode to a center position in the first direction of the fourth bonding electrode and a distance from a center position in the first direction of the fifth bonding electrode to a center position in the first direction of the sixth bonding electrode are matched in a range of from 90% to 110%.
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