| CPC G11C 29/4401 (2013.01) [G06F 11/1044 (2013.01)] | 20 Claims |
|
1. A memory device, comprising:
a memory cell array having a plurality of memory cells therein that span a plurality of rows, which are grouped into segments, and a plurality of columns, which are grouped into ticks, said ticks including normal ticks, and a spare tick that spans at least one redundancy column of memory cells in the memory cell array; and
a repair circuit configured to repair a first source address of a first failed column in each of a plurality of the segments with a first destination address of a pass column in a first normal tick, using a first source-destination (SD) flag signal, and then further repair the first destination address of the pass column with a first redundancy column within the spare tick that corresponds to the first destination address;
wherein the first SD flag signal indicates a first mapping relationship between the first source address and the first destination address, and a second mapping relationship between a second source address and the first destination address; and
wherein the second source address is a second failed column generated in the first normal tick.
|