US 12,334,170 B2
Operating and testing semiconductor devices
Taewook Park, Suwon-si (KR); Eunhye Oh, Suwon-si (KR); Jisu Kang, Suwon-si (KR); and Yongki Lee, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on May 9, 2023, as Appl. No. 18/314,508.
Claims priority of application No. 10-2022-0082139 (KR), filed on Jul. 4, 2022.
Prior Publication US 2024/0006008 A1, Jan. 4, 2024
Int. Cl. G11C 29/36 (2006.01); G01R 31/317 (2006.01); G01R 31/3193 (2006.01); G06F 11/10 (2006.01); G11C 29/00 (2006.01); G11C 29/02 (2006.01); G11C 29/12 (2006.01); G11C 29/42 (2006.01); G11C 29/44 (2006.01); G11C 29/52 (2006.01); G11C 29/56 (2006.01)
CPC G11C 29/36 (2013.01) [G01R 31/31703 (2013.01); G01R 31/3193 (2013.01); G06F 11/1048 (2013.01); G11C 29/022 (2013.01); G11C 29/42 (2013.01); G11C 29/44 (2013.01); G11C 29/4401 (2013.01); G11C 29/52 (2013.01); G11C 29/56008 (2013.01); G11C 29/76 (2013.01); G11C 29/78 (2013.01); G11C 29/808 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/3602 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of operating a memory device, wherein the memory device comprises a memory cell array including a normal area, a redundancy word line, and a redundancy area, the method comprising:
performing a plurality of program operations on the normal area based on a test pattern;
following each program operation, performing a read operation based on the test pattern; and
following each read operation,
detecting one or more error bits with respect to the test pattern,
identifying, for each error bit of the one or more error bits, a corresponding location of a cell containing the error bit among a plurality of memory cells included in the normal area, and
updating an error count for each identified location.