US 12,334,164 B2
Shift register, gate driving circuit and display apparatus
Yao Huang, Beijing (CN); and Ming Hu, Beijing (CN)
Assigned to Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Appl. No. 18/705,560
Filed by Chengdu BOE Optoelectronics Technology Co., Ltd., Sichuan (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Apr. 21, 2023, PCT No. PCT/CN2023/089909
§ 371(c)(1), (2) Date Apr. 28, 2024,
PCT Pub. No. WO2023/207808, PCT Pub. Date Nov. 2, 2023.
Claims priority of application No. 202210455761.0 (CN), filed on Apr. 24, 2022.
Prior Publication US 2025/0006284 A1, Jan. 2, 2025
Int. Cl. G11C 19/28 (2006.01); G09G 3/3266 (2016.01)
CPC G11C 19/28 (2013.01) [G09G 3/3266 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A shift register, comprising: an input module, a first output module, a second output module, a first control module, a second control module, a third control module, a fourth control module, and an energy storage module;
the input module is connected with an input signal terminal, a first clock signal terminal, and a second node, and is configured to provide an input signal of the input signal terminal to the second node under control of a first clock signal of the first clock signal terminal;
the first output module is connected with a first power supply signal terminal, the second node, and an output signal terminal, and is configured to provide a first power supply signal of the first power supply signal terminal to the output signal terminal under control of a voltage of the second node;
the second output module is connected with a second power supply signal terminal, a first node, and the output signal terminal, and is configured to provide a second power supply signal of the second power supply signal terminal to the output signal terminal under control of a voltage of the first node;
the first control module is connected with the second power supply signal terminal, the second node, and the first node, and is configured to provide the second power supply signal of the second power supply signal terminal to the first node under control of the voltage of the second node;
the second control module connected with the first clock signal terminal, a third node, and the first node, and is configured to provide the first clock signal of the first clock signal terminal to the first node under control of a voltage of the third node;
the third control module is connected with the input signal terminal, the second power supply signal terminal, a second clock signal terminal, and the third node, and is configured to provide the second power supply signal of the second power supply signal terminal to the third node under control of the input signal of the input signal terminal, and to provide the second power supply signal of the second power supply signal terminal to the third node under control of a second clock signal of the second clock signal terminal;
the fourth control module is connected with the first power supply signal terminal, the first clock signal terminal, the second power supply signal terminal, the second clock signal terminal, and a fourth node, and is configured to provide the first power supply signal of the first power supply signal terminal to the fourth node under control of the first clock signal of the first clock signal terminal, and to provide the second power supply signal of the second power supply signal terminal to the fourth node under control of the second clock signal of the second clock signal terminal;
the energy storage module comprises a first capacitor, and two ends of the first capacitor are respectively connected with the third node and the fourth node.