US 12,334,161 B2
Memory device and method of operating the same
Jong Hoon Lee, Icheon-si (KR); and Se Chun Park, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 20, 2022, as Appl. No. 17/970,079.
Claims priority of application No. 10-2022-0067450 (KR), filed on Jun. 2, 2022.
Prior Publication US 2023/0395169 A1, Dec. 7, 2023
Int. Cl. G11C 16/34 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01)
CPC G11C 16/3459 (2013.01) [G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/3404 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a plurality of memory cells;
a peripheral circuit configured to perform a verify operation that identifies threshold voltages of the plurality of memory cells by using a first verify voltage and a second verify voltage that has a higher voltage than the first verify voltage; and
a program operation controller configured to control the peripheral circuit, after the verify operation is terminated and during a period in which a pass voltage and a program voltage are sequentially applied to a word line coupled to the plurality of memory cells, to:
while the pass voltage is applied to the word line, apply a first control signal having a first voltage magnitude to a page buffer that is coupled to a first memory cell, among the plurality of memory cells, the first memory cell having a threshold voltage that is higher than the first verify voltage and lower than the second verify voltage, and
while the program voltage is applied to the word line, apply a second control signal having a second voltage magnitude that is lower than the first voltage magnitude to the page buffer.