US 12,334,158 B2
Pump discharge sequence improvements in external power supply mode for pulse recovery phases in non-volatile memory
Soo-yong Park, San Jose, CA (US); Pranav Chava, Folsom, CA (US); and Binh Ngo, Folsom, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Dec. 8, 2021, as Appl. No. 17/545,672.
Prior Publication US 2023/0178158 A1, Jun. 8, 2023
Int. Cl. G11C 16/30 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory chip controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic includes a charge pump, and wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
apply a program voltage from the charge pump to selected wordlines in NAND memory;
conduct a discharge of the program voltage from the charge pump; and
maintain a connection between the selected wordlines and a pass voltage of the charge pump while the program voltage is being discharged.