US 12,334,156 B2
Memory device and method of operating the memory device
Jae Hyeon Shin, Icheon-si (KR); Chang Han Son, Icheon-si (KR); In Gon Yang, Icheon-si (KR); and Sung Hyun Hwang, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Apr. 18, 2023, as Appl. No. 18/302,728.
Claims priority of application No. 10-2022-0159060 (KR), filed on Nov. 24, 2022.
Prior Publication US 2024/0177775 A1, May 30, 2024
Int. Cl. G11C 16/28 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/0433 (2013.01); G11C 16/08 (2013.01); G11C 16/3459 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A memory device comprising:
a plurality of memory cells connected to a plurality of word lines arranged between a plurality of source select lines and a plurality of drain select lines;
a peripheral circuit configured to perform a program operation of programming data in selected memory cells among the plurality of memory cells; and
a program operation controller configured to control the peripheral circuit to apply a voltage, for turning on source select transistors connected to the plurality of source select lines, to the plurality of source select lines while applying a pass voltage to the plurality of word lines after applying a program voltage to selected word lines connected to the selected memory cells.