US 12,334,152 B2
Simultaneous programming of multiple sub-blocks in NAND memory structures
Ali Khakifirooz, Brookline, MA (US); Pranav Kalavade, San Jose, CA (US); Shantanu Rajwade, Santa Clara, CA (US); and Tarek Ahmed Ameen Beshari, Santa Clara, CA (US)
Assigned to SK Hynix NAND Product Solutions Corp., Rancho Cordova, CA (US)
Filed by Intel NDTM US LLC, Santa Clara, CA (US)
Filed on Mar. 25, 2021, as Appl. No. 17/212,792.
Prior Publication US 2022/0310160 A1, Sep. 29, 2022
Int. Cl. G11C 16/04 (2006.01); G06F 3/06 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/0483 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A memory chip controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
boost strings of a plurality of NAND sub-blocks to a pass voltage, and bypass a boost of an initial NAND sub-block in the plurality of NAND sub-blocks;
deboost a first subset of the boosted strings based on data associated with the plurality of NAND sub-blocks; and
simultaneously program the first subset while a second subset of the boosted strings remain at the pass voltage.